Phase frequency detectors (PFDs), phase locked loops (PLLs), and delay locked loops (DLLs) are used extensively in electronic circuits for a variety of functions related to signal communications. One function used in many communication systems includes clock and data recovery (CDR). Data transmissions may be sent to a receiver from a transmitter. The receiver can recover a clock signal from a received data signal, and then align the phase of a local receiver clock with the phase of the recovered clock signal. In some systems, a PLL or DLL can be used to perform clock phase alignment.
The phase detection circuits used in PLLs, DLLs, and other components are typically implemented by comparing the rising edges of two signals and generating a phase difference signal that is provided to further blocks in the system. These additional blocks may shift the phase of the local clock signal in accordance with the phase difference signal to align the phases of the signals. Some implementations provide multiple clock signals having different phases, where one of the clock signals is selected as being most closely aligned with the incoming signal.
However, in some implementations, the detection of the phase difference for the selection of an aligned signal is performed only once in order to reduce processing time. This can result in inaccuracies in the alignment of phases between the signals, if any noise or interference exists in the incoming signal. Noise or interference, such as jitter, in a digital transmission may make clock phase alignment more difficult. For example, jitter can include random and intermittent variations in a signal, such as phase shifts, that occur during transmission or from other sources.
Accordingly, apparatus and methods that accurately provide a signal having a phase aligned with an incoming clock or other particular phase, without significantly increasing processing time, would be desirable in many applications.